1. Field
The invention relates to a liquid crystal display (LCD) device and more particularly, to an array substrate for the LCD device and a manufacturing method of the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices have been spotlighted as a next generation display device having high value because of their low power consumption and good portability.
An LCD device uses alignment characteristics of liquid crystal molecules that change dependent upon the strength of an applied electric field. The LCD device displays a picture by varying transmittance of light incident from a lower side of the LCD device according to the arrangement (or rearrangement) of the liquid crystal molecules.
The LCD device includes an array substrate and a color filter substrate. Liquid crystal molecules are interposed between the array substrate and the color filter substrate. The array substrate includes gate and data lines that cross each other to define a pixel region, a thin film transistor that is formed at a crossing portion of the gate and data lines, and a pixel electrode that is formed in the pixel region. The color filter substrate includes a color filter layer that is composed of color filters, each of which corresponds to the pixel region, and a common electrode that is formed on an entire surface of the color filter substrate.
The thin film transistor receives signals from the gate and data lines, and the signal from the data line is provided to the pixel electrode through the thin film transistor according to the signal from the gate line.
Accordingly, the liquid crystal molecules are arranged according to an electric field induced between the pixel electrode and the common electrode, and a picture is displayed according to the arrangement of the liquid crystal molecules.
An array substrate for an LCD device of the related art will be described hereafter in detail with reference to figures.
FIG. 1 is an enlarged view showing a part of an array substrate for an LCD device according to the related art.
As shown in FIG. 1, a gate line 12 is formed in a first direction, and a data line 22 is formed in a second direction crossing the first direction. The gate line 12 and the data line 22 cross each other to define a pixel region P. A gate electrode 14 is formed at a crossing portion of the gate and data lines 12 and 22, and a semiconductor layer 16 is formed on the gate electrode 14. A source electrode 18 and a drain electrode 20 are formed on the semiconductor layer 16. The source electrode 18 extends from the data line 22 and overlaps a portion of the semiconductor layer 16. The drain electrode 20 is spaced from the source electrode 18. The gate electrode 14, the semiconductor layer 16, the source electrode 18 and the drain electrode 20 form a thin film transistor T. A pixel electrode 24 is formed in the pixel region P and is connected to the drain electrode 20.
Driving in the LCD device including the above-mentioned array substrate is affected by driving characteristics of the thin film transistor. More particularly, data signals input from the data line 22 may change due to parasitic capacitances induced between electrodes of the thin film transistor T.
The parasitic capacitances may be induced between the overlapped gate electrode 14 and source electrode 18 or between the overlapped gate electrode 14 and drain electrode 20. A parasitic capacitance induced between the overlapped gate electrode 14 and drain electrode 20 may be commonly designated as Cgd. The parasitic capacitance Cgd changes according as an overlapped area of the gate electrode 16 and the drain electrode 20 varies, and the change of the parasitic capacitance Cgd increases flicker or non-uniformity in images.
The change of the parasitic capacitance Cgd may be caused by misalignment while the source and drain electrodes are formed on the semiconductor layer. That is, since the source and drain electrodes 18 and 20 may move up and down or left and right due to the misalignment, an overlapped area between the gate electrode 14 and the source and drain electrodes 18 and 20 may be changed, thereby causing the change of the parasitic capacitance.
The changed parasitic capacitance Cgd changes an offset voltage ΔVp. The offset voltage ΔVp is unavoidable in a structure of the LCD device but is adjustable. However, if the offset voltage ΔVp is non-uniform, it is not effective to adjust the offset voltage ΔVp.
By newly designing the gate, source and drain electrodes of the thin film transistor, several trials have been made to overcome bad driving of the thin film transistor due to misalignment during manufacturing processes.
FIGS. 2 to 5 illustrate several structures of thin film transistors according to the related art.
FIG. 2 shows a thin film transistor having a U shape channel.
In FIG. 2, a source electrode 18 and a drain electrode 20 are formed over a gate electrode 14, which is a part of a gate line 12, and are spaced apart from each other. The source electrode 18 and the drain electrode 20 expose an active layer 16 in a U shape, thereby forming a U shape channel. The source electrode 18 has a U shape and the drain electrode 20 has a rod shape. One end of the drain electrode 20 is enclosed by the source electrode 18. The source electrode 18 is entirely disposed within the gate electrode 14 from a plan view, and the drain electrode 20. The drain electrode 20 is formed in a direction crossing the gate electrode 14, more particularly, the gate line 12.
In the above structure, the ratio of width to length of a channel may be large, thereby improving driving properties of the thin film transistor. Since the source electrode 18 is disposed within the gate electrode 14, an overlapping area of the source electrode 18 and the gate electrode 14 scarcely changes even if misalignment occurs during the processes.
However, an overlapping area of the drain electrode 20 and the gate electrode 14 still changes when misalignment occurs up and down in the context of the figure.
FIG. 3 shows a thin film transistor having another U shape channel, which is rotated clockwise about 45 degrees with respect to the U shape channel of FIG. 2. In FIG. 3, the drain electrode 20 has an angle of about 45 degrees with respect to the gate line 12. The gate electrode 14 protrudes from the gate line 12, and has an inclined side, which overlaps the drain electrode 20, with respect to the gate line 12.
In the structure of FIG. 3, an aperture area of a pixel region may be increased, but an overlapping area of the drain electrode 20 and the gate electrode also may change.
FIG. 4 shows a thin film transistor having another U shape channel, which is rotated clockwise about 90 degrees with respect to the U shape channel of FIG. 2. In FIG. 4, the gate electrode 14 protrudes from the gate line 12, and has sides substantially perpendicular to the gate line 12.
In the structure of FIG. 4, an overlapping area of the drain electrode 20 and the gate electrode 14 changes by rather a large amount when misalignment occurs.
FIG. 5 shows a thin film transistor having an L shape channel. In FIG. 5, the source electrode 18 has an L shape, and the drain electrode 20 is spaced apart from the source electrode 18 such that an L shape side of the drain electrode 20 faces the source electrode 18. In the structure of FIG. 5, an overlapping area of the drain electrode 20 and the gate electrode 14 also changes by a rather large amount when misalignments occur up and down or left and right in the context of the figure.
The above-mentioned structures may improve driving properties of the thin film transistor, but may cause changes in the overlapping area of the gate electrode 14 and the drain electrode 20 when misalignments occur.